AI Copilot for Hardware Verification — Built in India

Stop staring at waveforms, guessing what broke.

Verinox reads your Verilog, generates the testbench, and helps you trace why a signal misbehaved — before you open Verdi.

Request Early Access See the Demo

Phase 1 live · running on local models, no RTL leaves your machine

tb_top.vcd ● anomaly detected

4+ engineer responses across r/VLSI & r/chipdesign

Reviewed on Siemens Verification Academy, with feedback from AVAQ Semiconductor

Built for DV engineers & VLSI students across India

// problems we validated

The four things that eat a verification engineer's week

Every pain point below came from real conversations with DV engineers — not a feature brainstorm.

Tracing the "why" behind a failure

A waveform shows what happened. Verinox works backward from the failing signal to the RTL condition that caused it.

Verdi grinding to a halt

Large dump files shouldn't mean five-minute load screens. Verinox works off targeted signal slices instead of the full dump.

Not knowing which signal to trace

On a wide bus with hundreds of nets, Verinox narrows the search to the handful of signals actually involved in the failure path.

Simulations that hang, silently

No assertion fired, no error printed, sim just stalls. Verinox flags the last active driver before the stall so you're not guessing.

// how it works

From module to testbench, in one pass

Phase 1 is live today. Everything runs locally against your RTL — nothing is uploaded.

01
Drop in your Verilog module

Paste or upload any module — Verinox parses ports, parameters, and clocking without needing a spec.
02
Verinox reads the intent

A local CodeLlama model, run through Verinox's Flask engine, infers reset behavior, handshakes, and edge cases from the RTL itself.
03
Get a runnable testbench

A complete, simulation-ready testbench is generated — stimulus, checkers, and clock/reset boilerplate included.
04
Debug what fails (Phase 2)

The upcoming Simulation Debug Assistant traces failures back through the waveform automatically.

// live in phase 1

The Testbench Generator, today

This is the actual interaction — a module in, a self-checking testbench out.

localhost:5000

module fifo_ctrl #(parameter DEPTH = 16) (
  input  wire        clk,
  input  wire        rst_n,
  input  wire        wr_en,
  input  wire        rd_en,
  input  wire [7:0]  data_in,
  output reg  [7:0]  data_out,
  output wire        full,
  output wire        empty,
  output wire        almost_full
);
  // synchronous FIFO, DEPTH-entry
  ...
endmodule

module tb_fifo_ctrl;
  reg clk = 0;
  reg rst_n, wr_en, rd_en;
  reg [7:0] data_in;
  wire [7:0] data_out;
  wire full, empty, almost_full;

  fifo_ctrl #(.DEPTH(16)) dut (.*);

  always #5 clk = ~clk;

  initial begin
    rst_n = 0; wr_en = 0; rd_en = 0;
    #12 rst_n = 1;
    // directed write/read + almost_full check
    repeat (20) begin
      @(posedge clk);
      wr_en <= $urandom_range(0,1);
      rd_en <= $urandom_range(0,1);
    end
    #50 $finish;
  end
endmodule

// fair questions

Why not just use ChatGPT or Claude?

A reasonable question. Here's the honest answer.

Can't a general AI model already write a testbench?

For a quick, rough draft — yes, and we won't pretend otherwise. But most DV teams can't paste proprietary RTL into a general chatbot in the first place; it's an IP and compliance risk, not a preference. Verinox runs locally through Ollama, so your module never leaves your machine. That's the actual blocker Verinox removes.

Does my RTL ever get uploaded anywhere?

No. Phase 1 runs on Flask + Ollama + CodeLlama on your own machine — there's no cloud call, no external API, no copy of your module sitting on a server somewhere.

What can Verinox do that a general prompt can't?

Testbench generation is the easy part. The harder problem — tracing a waveform failure back to the RTL condition that caused it — needs a tool that actually reads your simulation dump and understands your DUT's signal relationships. That's what Phase 2, the Simulation Debug Assistant, is built for, and it's not a copy-paste-into-a-chatbot task.

Is Verinox open source?

Not yet — it's on the roadmap. For now, reach out through the contact form and we'll run your module through it directly.

// the path to a full copilot

Five phases, one direction

Verinox is being built in public, phase by phase, with DV engineers shaping what comes next.

Testbench Generator

Live

Generate a complete, runnable testbench from any Verilog module.

Simulation Debug Assistant

Trace a failing signal back to the RTL condition that caused it.

Coverage Analyzer

Planned

Surface coverage holes and suggest the stimulus to close them.

UVM Environment Generator

Planned

Scaffold a UVM environment — agents, sequences, scoreboard — from your DUT.

Full AI Verification Copilot

Vision

One assistant across the entire verification flow, from testbench to signoff.

// get in touch

Try Verinox on your own RTL

Early access is limited while Verinox runs locally. Tell us what you're verifying and we'll reach out.

For DV engineers & VLSI students
Runs on Flask + Ollama + CodeLlama, local-first
Status Phase 1 shipped, Phase 2 in progress
LinkedIn /in/aditi-mahindrakar